200MS/s 10bit SAR ADC with 1.5bit redundant acceleration

This paper presents a low power 10-bit 200MS/s successive approximation register analog-to-digital converter (SAR ADC) with 1.5bit redundant acceleration. In this design, technique of 1.5bit redundant acceleration is used in second bit of SAR ADC, which reduces the building waiting time of first bit without other comparison clock consumption. To realize low power, a brand-new 3-D 1-fF MOM unit capacitor is used as basic capacitor cell of capacitor array. The design is fabricated in TSMC IP9M 65nm LP CMOS technology. At the same sampling rates of 200MS/s, the simulation of proposed SAR ADC achieves an ENOB of 9.84bit, an SNDR of 59.8dB, an SFDR of 67.5dB and power consumption of 0.58mW under Nyquist sampling. The FOM of the SAR ADC is low to 2.83fJ/conv.