A RISC core design for an ATM network interfaces

The embedded RISC core can be used efficiently to design high-speed scalable ATM network interfaces. Such core could also make the design of these interfaces simple, shorten the developing cycle and reduce their developing cost. In this paper, we have studied the design issues related to reduced instruction set computer (RISC) core and specifically for high-speed ATM host-network interfaces applications. We have investigated the processing and the instruction types that the RISC core is usually performed in addition to its structure.