Analysis of the Effect of TSV-Induced Stress on Devices Performance by Direct Strain and Electrical Measurements and FEA Simulations

A well-documented effect of the mechanical stresses generated by 3-D IC packaging on the performance of electrical circuits, in some cases leading to their parametric failure, can be controlled by means of stress assessment EDA tools. Verification and calibration of the layout engineered stress models are traditionally performed on the basis of electrical data demonstrating the stress-induced changes in transistors' drain currents. This paper demonstrates the validity of such an approach in the case of chip-package interaction (CPI)-induced stresses. Through-silicon vias (TSV) were chosen in this paper as a well-controlled stress source. Specially designed test-structures were used for measurements of TSV-induced strains in FET channels by means of the transmission electron microscopy/convergent beam electron diffraction technique. Measured strains were used for calibrating the developed finite-element analysis model of TSV-induced stress. The calibrated stress model was employed for calculating the TSV-induced drain current changes in the nearby devices in the test structures designed for electrical measurements. The demonstrated good fit between the calculated and measured current changes validates the use of electrical measurements for calibrating CPI stress assessment models.