A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization

This work describes a Nyquist rate ADC based on a two-step voltage and time quantization technique which can reduce power consumption and improve scaling immunity for high resolution applications. The hybrid two-step approach uses a successive approximation register (SAR) ADC for coarse quantization in the voltage domain, and a time-to-digital converter (TDC) for fine quantization in the time domain. The residue amplifier is suited for deep submicron CMOS due to its low gain and small output swing requirements, allowing the use of a single stage architecture. A 20MS/s prototype was designed and implemented in 180nm CMOS. Measurement results demonstrate an SNDR of 73dB. Operating with a reference voltage of 1.6V and a TDC supply of 1.0V, the total power is 1.28mW. This results in a Walden figure-of-merit (FOM
_W
) of 17.4 fJ/conversion-step.