Integration of 3 level air gap interconnect for sub-quarter micron CMOS

A three-level interconnect structure using an air gap process has been successfully fabricated. The practical use of air gap interconnects has been proved by evaluating via chain yield and EM properties. The RC delay time is reduced by 38% as compared with that of Al-SiOF. The circuit performance has been found to be superior to those of other low-k interconnects, including Cu-SiOF. This air gap process is quite promising for sub-0.25 /spl mu/m CMOS technology.