The implementation of high-speed data transmission for 8B/10B protocol on FPGAs

The paper is to implement high-speed serial communication between FPGAs with 8B/10B protocol. High-speed data transmission or data bus often use 8B/10B protocol, such as Serial ATA, PCI Express, Fiber Channel, Internet. In general the development platform of FPGA has built-in 8B/10B IP core, such as the Quartus II and ISE, i.e. the 8B/10B IP core will be limited by different platforms. In this paper, an 8B/10B open source will be employed to solve this problem and applied to the merger board and universal trigger board of KEK [1] Belle II [2] experimental trigger system for connection testing where the transmission data rate is successfully achieved up to 3.125 Gbps. The testing results and comparisons among Aurora 8B/10B, Belle II 8B/10B and 8B/10B open source protocols will be included.