Design of 8 bit, 1633µm2, 444µW squarer hardware for high performance VLSI applications

In this paper, a new scheme for design and VLSI implementation of squarer circuits is proposed. The proposed design is based on further analysis and modification of squaring function's mathematical expression and provides high efficiency in hardware implementation. This improvement is based on two techniques, first, algebraic rearrangement of each result bit, and second, using anticipated symmetry from previously calculated results and applying it for other parts of the circuit. The proposed squarer has been implemented in TSMC 180nm CMOS technology and evaluation results demonstrates 14 percent reduction in die area, 18 percent reduction in static power consumption and also minor improvement in performance compared to conventional squarer.