Interconnect technology and design implications for future ASIC and system-on-a-chip (SOC) implementations

Back-end-of-the-line (BEOL) interconnect technology is undergoing a rapid transformation as a result of the projected impact on IC performance at decreasing minimum feature sizes. As a result, design complexity is becoming the gating item in leading edge IC products, leading to increasing design reuse of IC functional building blocks (i.e. macrocells and intellectual property (IP) cores), particularly for advanced application specific ICs (ASICs) and system-on-a-chip (SOC) implementations. Virtual Design Environment (VDE) software developed for complex printed circuit boards will expand to the chip level as SOC implementations (and advanced ASICs) incorporate increasing use of IP cores and increasingly complex wiring designs. IC manufacturing operations will become increasingly involved in providing and licensing IP cores in support of this evolving design methodology.