Double fault tolerant full adder design using fault localization

In the era of advanced microelectronics, rate of chip failure is increased with increased in chip density. A system must be fault tolerant to decrease the failure rate. The presence of multiple faults can destroy the functionality of a full adder and there is a trade-off between number of fault tolerated and area overhead. This paper presents an area efficient fault tolerant full adder design that can repair single and double fault without interrupting the normal operation of a system. In this approach, self checking full adder is used detecting the fault based on internal functionality. This makes the method efficient in term of area and number of fault tolerated when compared to the existing designs.