A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET

This brief presents a 4-GS/s single channel folding flash analog-to-digital converter (ADC) designed to be time-interleaved for wireline receivers in 16-nm FinFET CMOS. The resolution of the ADC is scalable to enable power savings depending on link modulation format (2 PAM/4 PAM) and link loss. A 1-bit folding stage determines the MSB, while the LSBs are determined by a 5-bit full flash where each comparator can be individually enabled/disabled. At 6-bit resolution, the ADC including a variable gain amplifier achieves an SNDR of 30.7 dB and an SFDR of 40.6 dB at Nyquist frequency while consuming 34.4 mW from a 0.9-V supply, yielding an FOM of 303 fJ/conv-step. At lower resolutions of 5, 4, and 3 bits, the FOM remains low at 295, 320, and 399 fJ/conv-step, respectively, at Nyquist frequency.