Clock tree synthesis for heterogeneous 3-D integrated circuits

Heterogeneous integration of disparate device planes is a benefit of through-silicon-via based 3-D integrated circuits (ICs). Clock delivery for heterogeneous 3-D ICs requires novel circuit techniques and algorithms as compared to 2-D and even homogeneous 3-D ICs. Novel algorithms for topology generation (heterogeneous 3-D balanced bipartitioning) and for embedding of a clock tree in a heterogeneous 3-D stack (heterogeneous 3-D deferred merge and embedding) are described. The algorithms are applied to a two-tiered heterogeneous stack of dies with configurations using the 28 nm, 40 nm, and 65 nm technology nodes. The results are analyzed against existing process agnostic clock tree synthesis algorithms for 3-D ICs, showing a reduction of 7% in power consumption, 6% in delay, 4% in buffer count and 4% in wirelength.