Calibration, bias and monitoring system for the VFAT3 ASIC of the CMS GEM detector

VFAT3 is the last version of a family of multichannel trigger and tracking ASICs designed for the upgrade of the CMS experiment in the LHC. The chip has been developed to provide fast trigger information from the readout of gas particle detectors improving the resolution of the time measurement. The VFAT3 architecture comprises 128 analog channels, each one composed by a low noise and low power charge sensitive amplifier, shaper and constant fraction discriminator. The comparator output is synchronized with the LHC clock and sent both to a fixed latency path for trigger signal generation and to a variable latency path for storage and readout. The front-end amplifier is programmable in terms of gain and pulse shaping time, in order to adapt it to a wide range of gaseous detectors as well as silicon detectors. The chip also comprises a programmable calibration system that can provide both voltage and current pulses. There are also two internal 10 bit ADCs for the monitoring of the internal bias references. The digital logic provides trigger generation, digital data tagging and storage, data formatting and data packet transmission with error protection on 320Mbps e-link. The digital design is triplicated in order to improve the radiation hardness of the system. A first run of the chip of 9.1×6.1mm
²
in 130nm technology node has been submitted and produced. Chip architecture, measurements and characterization of the calibration, bias and monitoring system will be shown.