A 1 V 6 b 50 MHz current-interpolating CMOS ADC

A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.