Study on defect reduction for high aspect ratio etch process

Increasing data needs much larger memory capacity. One of the Flash Memory Solution is Vertical NAND (V-NAND) Flash Memory. In order to fabricate this device, a high aspect ratio hole must be made in the channel hole through the etching process after multilayer thin film deposition. In order to obtain high aspect ratio etch, process condition should have high RF power, high flow rate of polymer gas, and long process time. This harsh etch condition results in high ion energy and lots of polymer production. It can create defects like fluorocarbon polymer and arcing. In this study, we studied arcing mechanism. Here we defined various margins for arcing-free and optimized the focus ring. And we improved pumping conductance for polymer discharge. This study removed defects and obtained arcing-free during V-NAND etch process