Innovative scalable design based care area methodology for defect monitoring in production

The use of design-based care areas on inspection tools [1, 2] to characterize defects has been well established in recent years. However, the implementation has generally been limited to specific engineering use cases, due to the complexity involved with care area creation and inspection recipe setup. Furthermore, creating, organizing, optimizing and auditing all these care areas per inspection step and per device can be time-consuming. In this work we demonstrate a novel methodology for the implementation of NanoPoint™ care areas across all inspection steps in semiconductor process flow, using a technology-specific set of care area generation rules, rather than rules targeted to particular defect of interest (DOI). This approach enables optimal recipe sensitivity across the entirety of a chip, by segmenting care area coverage into high-sensitivity, intermediate-sensitivity and low-sensitivity regions based on pattern density. Furthermore, this methodology is scalable in nature which means that the care area generation rules are defined only once per technology node, and thus, can enable automated care area generation for any chip design within a technology node, with no user input required. Inspection recipes created with this type of care area demonstrate consistent sensitivity for cross-product defectivity analysis in a high volume manufacturing (HVM) wafer fab.