A gate-quality dielectric system for SiGe metal-oxide-semiconductor devices

The authors present a high-quality dielectric system for use with Si/sub 1-x/Ge/sub x/ alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO/sub 2/ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si/sub 1-x/Ge/sub x/ layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si/sub 1-x/Ge/sub x/ channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets.<
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