Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA

Triple Modular Redundancy (TMR) is the most widely used technique to increase the reliability of SRAM-based FPGAs. In this paper, we investigate the application of TMR directly in C language-based algorithms to be synthesized using High Level Synthesis (HLS) to generate hardened Register Transfer Level (RTL) designs. We analyze four different TMR designs implemented into a 28 nm SRAM-based FPGA from Xilinx. Fault injection campaigns were performed aiming to analyze the probability of errors in those hardened architectures. We compare the information of essential bits delivered by the vendor with the critical bits provided by fault injection. Results show that the TMR technique applied at HLS level is capable of efficiently mask errors, reducing the number of critical bits by 30 times on average. Concerning TMR designs, the area overhead is 2.4 times on average, while performance overhead is 2.0 times when pipeline optimization is used.