Investigating the implementation of a block structured processor architecture in an early design stage

When designing a new micro-architecture, it is difficult to estimate the influence of the architectural parameters on clock period and chip area. In this paper, we use automatic synthesis to investigate the implementation of a novel processor architecture, namely a block structured instruction set architecture (BSA). In a BSA, instructions are statically grouped into fixed-length blocks by the compiler and the execution policy within a block is data-flow. The use of automatic synthesis is forced by the fact that a broad design space is investigated in an early design stage. The three parameters that we specifically focus on are blocksize, instruction selection window size and issue width. Various pipeline configurations are investigated. Moreover, we investigate the effect of technology scaling on the selection of the best architecture and pipeline configuration; we consider both a 0.8 /spl mu/m 2-metal layer CMOS technology and a more advanced 0.25 /spl mu/m 6-metal layer CMOS technology. From this paper we can conclude that a BSA has several implementational benefits over traditional architectures due to the partitioned design and the reduced wiring delays.