Simultaneous switching noise modelling and characterization in production environments

Predicting and optimizing the impact of simultaneous switching noise (SSN) on timing and voltage margins in production environments require an accurate and robust modelling methodology. Such a methodology requires high fidelity representing of the physical structures at the chip, package and board level. Here, a modified merge bit approach is used to generate an accurate current profile of the full-chip under realistic switching conditions. The loading effects of the automatic test equipment (ATE) are fully modelled to consider trace-plane coupling as well as socket parasitics in the production environment. To address the extensive computation time of this elaborate analysis, power aware IBIS modelling is employed to accelerate the simulations. Measurement results are presented to provide confidence of this comprehensive and fast simulation methodology.