Simulation and implementation comparison of two 3 V-5 V 14-bit current-steering wideband CMOS DACs

The influence of matching and output impedance on the performance of wideband current-steering DACs has been discussed. Both mathematical, simulated, and measured results was presented. Formulas and considerations were verified with simulations and measurements. A faster prediction of the performance using Matlab models can be achieved by using the error modeling. An SFDR larger than 74 dBc was measured at a sample frequency of 5 MHz. By reducing internal capacitance, simple improvement of matching, and reducing wire resistance, an SFDR improvement of 6-24 dB was found.