Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model

In this paper, we present a timing model of flit transactions for primitive components in irregular interconnect fabrics. Based on the model, we then develop a fast timing simulator for on-chip interconnects with a 100% cycle accuracy when validated with an industrial RTL implementation. With our timing simulator, we can design and optimize architectures of interconnects by adjusting topologies, FIFOs, outstanding buffers, data widths, and clocking. In a case of high-performance networking SoC, the proposed approach can explore the design space effectively, minimizing the latency of intercommunication to 43.6% as compared with the initial architecture. The area cost can also be reduced to 88.1% at the same time.