Dynamic element matching for highly linear digital-to-analog conversion

This paper presents a performance analysis of a dynamic element matching technique for low harmonic distortion digital-to-analog converters (DACs). The technique employs simple binary switches controlled by pseudo-random bit sequences to make appropriate selections in a bank of unit DAC-elements whose outputs are summed to form the output of the composite DAC. Harmonic distortion resulting from static mismatches of the unit DAC-elements is eliminated at the expense of an increased DAC noise floor. The analysis provides an expression for the power of the white DAC noise in terms of certain time-average means of the input and the static mismatch errors, and IC fabrication yield estimation data of the noise power are presented for selected DAC bit resolutions. Furthermore, a comparison with other reported DEM techniques for low harmonic distortion DACs shows that the technique considered here is of least hardware complexity.