Minority Carrier Disturb in Thyristor Memory Arrays and a Novel Cell Design for High Density DRAM

Inter-cell disturb from minority carriers is found to be one of the major problems for scaling cross-point vertical Thyristor arrays. Cell designs with minority carrier lifetime killers and deep trench isolations are either ineffective or difficult to manufacture. This paper discloses a novel MBW-VLT cell that achieves a 5F2 bit cell area, is compatible with existing DRAM fabrication tools, and devoid of any minority carrier disturbance. A well calibrated TCAD simulator is used to fully verify both DC and AC operations of cell strings.