Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Negative Bias Temperature Instability (NBTI) is due to interface trap generation (ΔN
_IT
) and trapping of holes in gate insulator traps (ΔN
_HT
). However, the isolation methods and the relative dominance of ΔN
_IT
and ΔN
_HT
, time constants of ΔN
_IT
and ΔN
_HT
for stress, recovery and associated temperature (T) activation, and whether ΔN
_IT
recovers or remains permanent after stress, are widely debated. The resolution of such disputes is necessary to develop a reliable NBTI model. This work uses carefully designed measurements and simulations to resolve the aforementioned disputes. The contribution of ΔN
_IT
and ΔN
_HT
on overall threshold voltage shift (ΔV
_T
) is determined. Kinetics of ΔN
_IT
and ΔN
_HT
during stress and recovery, T activation and associated time constants are verified in both large and small area devices. Existing theoretical models for ΔN
_IT
and ΔN
_HT
are benchmarked and validated against DC and AC experiments. Capability of the existing models for predicting end-of-life ΔV
_T
is demonstrated.