Investigation of read disturb error in 1Ynm NAND flash memories for system level solution

Read-disturb characteristics in 1Ynm NAND flash memories have been investigated. The error regularity among word-lines is observed in 1Ynm (2
^nd
generation below 20nm) triple-level cell (TLC) NAND flash. Consequently, unreliable page which exceeds error-correcting code (ECC) capability is occurred. To optimize ECC capability, system level solution with Bose-Chaudhuri-Hocquenghem (BCH) ECC is introduced. By adding parity bit to the unreliable pages for ECC calculation, a correctable bit-error rate (BER) can be increased by 1.3-times.