Error recovery of low resistance state in 40nm TaOx-based ReRAM

Error recovery effect of low resistance state (LRS) has been observed for the first time in set/reset cycling endurance in 40nm TaO
_x
-based ReRAM cell. LRS error cells, which have an abnormally high resistance, are recovered to normal LRS by the relaxation time for error recovery between set and reset. This phenomenon can be explained by oxygen vacancy (VO) diffusion from TaO
_x
layer to reconstruct the conductive filament in error cells. Based on this phenomenon, the bit error rate (BER) in ReRAM for the future high speed storage system is reduced by the dispersed data writing with the wear-leveling.