High performance picture-in-picture (PIP) IC using embedded DRAM technology

In this paper the next generation of a low cost, high performance single-chip picture-in-picture IC is presented. This chip is produced in a 0.35 /spl mu/ eDRAM technology and integrates a digital multistandard color decoder, embedded DRAM, A/D and D/A converters as well as a data slicer for caption services. The paper deals with the digital video signal processing for color decoding with asynchronous sampling and the compensation of the skew. A new algorithm for a jointline-free true frame display was developed. The chip allows a smooth scaling from 1/81 to 1/4 of full-screen picture size and implements a data compression algorithm for splitscreen modes.