High speed implementation of piecewise-quadratic Takagi-Sugeno systems

An extremely time-efficient, accuracy-controlled algorithm for the computation of piecewise-quadratic Takagi-Sugeno inferences is presented which is suitable for implementation on advanced DSPs. Details of the coding of such procedure on an high-end VLIW fixed point DSP are given to demonstrate speed benefits. As an example, an inference depending on 8 inputs can be computed in less than 2 /spl mu/ when the trivial, dimensionality-cursed approach takes not less than 30 /spl mu/ on the same 200 MHz device.