Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs

High-Level Synthesis (HLS) has emerged as a leading technology to reduce the design time and complexity that is associated with reconfigurable systems. In order to maintain the productivity promised by HLS, it is important that the designer can debug the system in the context of the high-level code. Currently, software simulations offer a quick and familiar method to target logic and syntax bugs, while software/hardware co-simulations are useful for synthesis verification. However, to analyze the behaviour of the circuit as it is running, the user is forced to understand waveforms from the synthesized design.