Low-voltage flip-flop-based frequency divider up to 92-GHz in 130-nm SiGe BiCMOS technology

This paper presents a flip-flop-based pseudo-current-mode logic (CML) 2:1 frequency divider designed in 130 nm SiGe BiCMOS technology. We use an auxiliary transistor to increase the current thru the data pair, known as the “keep-alive” bias technique. Thereby one can easily control the asymmetry of the period by tuning the gate voltage of the auxiliary transistor. This enables tunable divider's self-oscillation frequency (SOF) enhancement. The effect is confirmed in measurement by showing that the highest division frequency can be increased by up to 25 GHz. The frequency divider operates from 14 GHz to 89 GHz consuming 21 mA from a 1.2 V supply, or from 2 GHz to 92.5 GHz consuming 37 mA from a 1.5 V supply. To the authors' knowledge, the presented divider achieves the highest ratio of frequency range to power consumption reported to date.