Correlation between mechanical material properties and stress in 3D-integrated silicon microstructures

Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical connections for signaling and power delivery through the silicon (Si) carrier used in 3D-stacked microstructures. As a limitation, TSVs induce locally thermomechanical stress in the Si lattice due to a mismatch in the coefficients of thermal expansion between Si and the TSV-filling metals and therefore enforce temperature related expansion and shrinkage during the annealing cycle. This temperature-induced crowding and relaxation of the Si lattice in proximity of the TSV (called “keep-out-zone” forbidden for active device positioning) can cause a variety of issues ranging from stress-induced device performance degradation, interfacial delamination or interconnect failures due to cracking of the bond or even of the entire Si microstructures at stress hotspots upon assembly or operation. Additionally also the interconnect structures induce stress that will overlap with the TSV induced stress. In this paper, we investigate layout and material related stress profiles from a theoretically and experimentally point of view. Applied on a novel dual-shell Si interposer platform including liquid-cooling technology based on fluidic micro-channels aiming at high performance heat removal (i.e. as dissipated from HPC-processors on top of the device). Additionally while using water as coolant certain sealing structures have to be integrated to circumvent electrical shorts and electrolysis. Initially we investigate experimentally the mechanical properties of the electro-plated copper used for the fabrication of the actual devices. In a second step we did the simulation of strain the strain brought into the Si lattice. The process- and morphology-dependent stress-strain curve is a crucial input parameter for the following simulation as deviations at small strain levels have a major impact on the outcomes. Tensile testing for 5, 15 and 20 μm thick Cu samples were performed with 15 μm thickness being the nominal diameter of the TSVs used in the later studies. This macroscopic material behavior is correlated with the microstructure of the material as determined by Scanning Electron Microscopy. Experimentally, the stress profile in Si around a certain interconnect and sealing structure is measured by fibDAC, a method for investigation of stress relaxation. A comparison of measurements and Finite Element Analysis (FEA) will be provided, revealing good qualitative and quantitative correlations. Finally, we estimate reliability risks, an assessment which is based on the combined thermo-mechanical stress determinations by experiment and theory.