The design and implementation of a reconfigurable convolution operator based on APU

In order to achieve fast IC design, reduce development cycle and cost, Key Lab of Integrated Microsystems in Peking University proposed Array Processing for Unification Architecture(APU) which consists of four kinds of operators: computation, data path, control and MEM operators to replace the configurable logic block in current FPGA fabric. In this paper, a reconfigurable convolution operator based on APU, is presented which is used to convolutional neural network computing. The reconfigurable convolution operator is with more coarse-grain and function changeable than APU. And the process of operator synthesis is verified by simulation-based verification and formal verification separately. With the verification method proposed in this paper, certainty and completeness have been achieved. The results show that compared with the hardware design at the cost of resources based APU, this methodology can obtain hardware of suitable performance with regular structure with the cost of 34.08% less area and 25.26% lower power.