FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability

Physical Unclonable Function (PUF) has now become a core lightweight hardware-intrinsic cryptographic primitive for device identification and authentication to secure edge computing in Internet of Things (IoT). The main challenge in most delay-based PUF implementations is the rival of response uniqueness and reliability. Due to routing constraint, implementation of delay-based strong PUF on FPGA tends to have either poorer reliability under varying operational conditions or vulnerably high predictability. Therefore, the design of high quality strong PUF often entails tradeoff between reliability and unpredictability (including uniqueness and randomness). Arbiter PUF is one of the most popular structures for FPGA implementation. It suffers from relatively low reliability and high susceptibility to machine learning attacks due to the linearity of its cascaded switch mode delay representation model. To overcome both problems simultaneously, we dichotomize the challenges to winnow out the unreliably weak challenges and obfuscate the remaining reliable strong challenges to increase its unpredictability against machine learning attacks. The security A-PUF is hardened at the expense of small hardware and latency overhead in preprocessing the challenges.