The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping

As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of short-channel effects and improvement of on-state current is tradeoff in conventional ion implantation process. In this paper, we demonstrate p-type bulk Si fin field-effect transistors by using solid-source doping for better impurity profile in fin to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current. In this paper, impurity profiles in fin with two different kinds of anneal conditions after fin revelation (1000 °C 30 s and 1050 °C spike) are analyzed, and the better impurity profile at channel area is designed by 1000 °C 30-s anneal for better electrical characteristics. The anneal condition with the better impurity profile in fin shows mobility improvement at long gate length (1 μm) and short gate lengths (60, 70, and 80 nm); subthreshold slope and transconductance are improved at the same time. With those results, we conclude that a fabrication process flow of p-type bulk Si fin field-effect transistors to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current is established with 1000 °C 30-s anneal after fin revelation by using solid-source doping. At the same time, electrical characteristics variation is also suppressed in the case of 1000 °C 30-s anneal.