Analysis of routing algorithms generation for irregular NoC topologies

Network-on-Chip (NoC) is the most promising communication architecture for a scalable and high parallel System-on-Chip (SoC). Recent manufacturing technologies are very close to physical limitations increasing the number of faults during fabrication and operation; as a result, NoCs designed to be regular often will become irregular. Thus, the analysis of irregular topologies derived from regular ones is an important task in the NoC design. This work uses a tool that evaluates restriction paths of irregular NoCs to ensure deadlock freedom and generates analytical metrics for assessing the quality of routing at design time. We used a fault model for generating NoC topologies with faulty links, which allows exploiting manufacturing processes scenarios with 65 nm and 22 nm CMOS technology, from the links delay variability and spatial correlation strength. We also used a segmentation algorithm to avoid deadlocks. The experimental results show that the percentage of faults significantly increases with the spatial correlation strength, while the average distance between topological faults decreases. Furthermore, the greater the fault percentage gets, the longer the routing average distance becomes.