Modeling of Via Resistance for Advanced Technology Nodes

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step.