Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Process

In the via-middle process of 3-D integrated circuit manufacturing, through-silicon via (TSV) annealing causes mechanical stress not only to its surrounding structures, including liner and landing pad, but also the contacts nearby. This process may result in a noticeable pop-out in TSVs and/or contacts, thus complicating the subsequent chemical mechanical polishing (CMP). In addition, residual stress may cause delamination or crack. In this paper, we conducted detailed simulations of the residual stress and pop-out mechanisms for TSVs and neighboring contacts. Our primary focus was on the interplay of TSV-induced and contact-induced stresses and their combined impact on pop-out height. In addition, we conducted a sensitivity analysis of key parameters, including distance, plasticity, annealing temperature, and the distribution of neighboring contacts. This paper showed that these parameters notably affect the stress and the pop-out of TSVs and contacts. This in turn is expected to complicate the subsequent CMP steps. Finally, we applied the linear superposition method to predict stress and validated its accuracy by comparing the results with finite element analysis simulation. The results of the comparison demonstrated that the superposition method was accurate. Therefore, it could be used to predict the stress for full-chip design.