A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET

A low VMIN with assist technique and high speed novel word line strapping architecture specific to read/write dual-port (DP) SRAM compiler is realized in 10nm FINFET technology. We able to achieve the Vmin below 0.5V for the 1-2-4 high density 8T-SRAM using Reliability Aware Negative bit line Write Assist (RA-NBL) technique and reduced read margin of the SRAM cell recovered using Word line under drive technique. Bit-line is pulled to a required negative value in order to provide sufficient assistance for the write operation without stressing the write logic and SRAM array. The statistical simulation results show that Vmin improvement greater than 100 mv. RA-NBL enable low voltage operation along with improved performance at typical/higher voltage. A write performance improvement of 10-15 percent gained by not turning off WA for typical to high operating voltages as introduced the RA-NBL provides lesser negative bit line bump without compromising reliability and ageing keeping device with-in safe operating voltage range even at high voltage/temperature. Double patterning in DP SRAM creates inherited RC mismatch across different ports solved by introducing Dual port specific word Line Strapping techniques that's solved the performance mismatch issue across different ports and reduces memory access and cycle time up to ~150 ps and ~300ps respectively.