Implant and Anneal Technologies for Memory and CMOS Devices

Ion Implantation and Anneal processes are very important for Transistor Characteristics. Even scaling devices such as 3D structures require junction engineering involving implantation and anneal processes to boost device performance. This paper will discuss some key issues in the DRAM cell and peripheral transistor, and propose requirements of processes and hardware. Data were evaluated in Logic and CIS devices as well as in DRAM devices. The paper will conclude with suggestions of new approaches in DRAM device application.