DIPS for MIPS: an instrumented VHDL/Corba kernel for distributed learning in EECS

The paper presents a distributed interactive pedagogical simulator (DIPS) dedicated to EECS. The simulator implements a multimedia/Java/Corba instrumentation of the famous Patterson and Hennessy MIPS multicycle core. Each learner is responsible for one functional unit (Datapath, control FSM, memory), and has to mimic manually its behaviour by: (a) receiving required operations per clock cycle; (b) conducting the required operations by graphically manipulating icons in a user interface; (c) receiving feedback on the relationship between their operations and known valid operations produced by the reference VHDL kernel simulator. The key principle is the continuous comparison of the computer state vector produced by an integrated VHDL kernel simulator (i.e. the reference) to the one produced by the collaborative work of the learners over a LAN.