New Systolic Array Architecture for Finite Field Inversion

This paper proposes a new systolic array architecture to perform inversion operation in GF(2
^m
) based on a previously modified extended Euclidean algorithm. This architecture has low area and power complexities and it achieves a moderate speed. This architecture is explored by applying a regular technique to the inversion algorithm. The systolic architecture obtained has simple structure with processing elements that have local communication with each other. ASIC implementation of the proposed design and comparable published designs shows that the proposed design saves more area (ranging from 14.1% to 63.4%) and saves more energy (ranging from 22.9% to 81.9%) over the compared efficient designs that makes it more suitable for resource-constrained embedded applications that impose more constraints on area and power consumption.