A Comprehensive DC and AC PBTI Modeling Framework for HKMG n-MOSFETs

A physics-based modeling framework is proposed to calculate the threshold voltage shift (ΔV
_T
) in planar high-k metal gate (HKMG) n-MOSFETs for positive bias temperature instability (PBTI). Overall ΔV
_T
is estimated using the uncorrelated contributions from the trap generation (TG) and the electron trapping subcomponents. The time evolution of ΔV
_T
, measured using an ultrafast measure-stress-measure method during dc and ac stress and after dc stress, is predicted for different experimental conditions. The modeled TG component is verified by independent direct-current I-V method. The proposed model explains PBTI in differently processed HKMG gate stacks.