Architectural Enhancement of LEON3 Processor for Real Time and Feedback Applications

The trade-off between performance and power consumptionfor dynamic and complex applications is inevitable andis considered as a key design challenge for system architects. Performance statistics for hard real time systems must be readilyavailable for a feedback system, specifically for reconfigurablearchitectures. The feedback in terms of performance statisticscan be useful for run-time reconfiguration of a system drivenby various optimization algorithms. A system's performancecan be monitored at run-time using hardware performancecounters (HPCs) aiming to improve performance with minimaloverheads in terms of energy, cost and complexity. Therefore, this paper presents an enhanced version of LEON3 architecturewhich includes support for the performance monitoring scheme(PMS) to analyze dynamic events such as cache hit/miss ratioand the number of cycles consumed by running applications. This modification can be useful as performance evaluation isconsidered as a key metric in real-time reconfigurable systems. The significance of PMS is highlighted by various power relatedmathematical models to build throughput and energy awareembedded systems. This enhanced SoC has been tested withvarious standard benchmarks such as Dhrystone, Coremark, Stanford suite and MiBench suite. All the results have been testedwith simulator and with real hardware on Xilinx ML509 FPGAprototyping board. The result shows the error percentage of lessthan 7 when compared with TSIM. This enhancement can beuseful for real time space applications with a minimal hardwareoverhead of about 1-3% LUTS and 10.8% in case of Block RAMs.