Analysis and comparison of DDR3/DDR4 clock duty-cycle-distortion (DCD) for UDIMM and discrete SDRAM component configurations

In this paper, the clock duty cycle distortion (DCD) jitter will be investigated and the results will be compared for two channel configurations: using a general UDIMM topology and using discrete SDRAM component topology. These channel configurations will be simulated and analyzed for ISI effects, such as channel loss and reflection. The outcome of this investigation will show the primary factors that contribute to on-clock DCD in a most common DDR channel configurations. After analysis and comparison, the simulated differential clock DCD data will be provided while changing channel impedance corners due to the substrate manufacturing tolerance for package and PCB in a reflective discrete DRAM component and lossy UDIMM configurations. Finally, the simulation model-to-hardware correlation will be performed for each configuration. The simulated clock waveforms will be correlated with the measured waveforms for each configuration and the simulated differential DDR clock DCD analysis will be verified with the measured clock DCD jitter amount in actual system configurations.