The Impact of Self-Heating on HCI Reliability in High-Performance Digital Circuits

While many groups attribute the greatly accelerated (i.e., excess) HCI degradation in modern transistors to the difference between the peak temperature and the average temperature (ΔT
_L,Diff
= ΔT
^pk
_L
- ΔT
^avg
_L
≫ 0) in self-heated FinFETs and other multigate transistors under dc or low-frequency stress, others find no evidence of the ΔT
_L,Diff
-related excess degradation for ICs operating at high frequencies. In this letter, we resolve the puzzle by using a hierarchical electro-thermal device-circuit predictive model for HCI degradation to demonstrate that ΔT
_L,Diff
→0 beyond a technology-specific transition frequency (ω
_c
), and therefore, excess HCI degradation disappears at ω ≫ ω
_c
. The proposed analytical model directly correlates HCI performance to power pulse trains characterized by frequency (f) and power duty cycle (ξ) of a digital circuit. Self-heating will continue to reduce HCI-lifetime of surround gate transistors due to the increase of average temperature (ΔT
^avg
_L
), but the excess degradation caused by ΔT
_L,Diff
will not be a concern for high-speed digital circuits.