Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)

In the current mobile electronics market, there is a great demand of electronics products with better performance, smaller foot print and greater package functionality with a lower manufacturing cost. Smart phones and tablets are some of the portable electronics devices that require more functions, smaller form factor and reduced power consumption requirements [1]. To address these requirements, the Multi-Chip Fan-Out Wafer Level Package (FOWLP) technology promises an alternative technology for high performance and multi-die packaging in FOWLP technology [2]. In conventional flip chip assembly, the advantages of using Cu pillar and solder micro bumps are mainly because of it allows for fine pitch applications and superior power management in terms of thermal and electrical [3]. The major difference in using copper pillar with solder micro bumps is that the solder volume are significantly reduced on each solder bump. Furthermore, the lesser solder volume on the Cu pillar bumps makes it difficult for solder self-alignment during solder reflow process [4]. Hence it is critical that good chip placement accuracy is needed in the flip-chip bonder for good solder interconnect formation especially for our work in the new RDL-first FOWLP technology with multiple die and high pin count applications [5]. In this paper, we present the chip to wafer assembly for multiple die on the RDL-First FOWLP approach. Chip-to-Wafer assembly is a promising technology for high density package application to overcome the limitation of Wafer-to-Wafer boding in terms of die stacking process yield and bonding placement accuracy on wafers. Our test vehicle is a large multi-chip package of 20x20mm
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fabricated using the RDL-First FOWLP approach. There are 2400 I/Os on the FOWLP package. The C2W flip chip process is done to attach the 3 test chips onto the 3 layers RDL film onto the 12 inch glass carrier with sacrificial layer using the mass reflow method. The assembly process was optimized and samples are built to subject to JEDEC Moisture Sensitivity Test Level 3 for reliability assessment.