Gate prespacers for high density DRAMs

The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow the continued cell shrinkage with only limited shrinking of the channel length. In this paper, we present an integration scheme which allows for a larger gate polysilicon length for a given pitch thus improving array device leakage (by about one generation) for a given technology.