Implementation of a low power 128-point FFT

In this paper a low power 128 point fast Fourier transform (FFT) processor is implemented based on our new VLSI-oriented FFT algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. A new management of the on-chip memory further reduce its power consumption. This FFT processor has been designed in 0.6 /spl mu/m 3.3 V triple-metal CMOS process with an area of 10 mm/sup 2/. The chip is capable of computing a 128 point FFT every 3 /spl mu/s and the power dissipation is 400 mW at 50 MHz input frequency.