Approximate logic synthesis for FPGA by wire removal and local function change

Approximate computing is a new design paradigm targeting at error-tolerant applications. By allowing a little amount of inaccuracy in the computation, it could significantly reduce circuit area and power consumption. Several logic synthesis methods for approximate computing were proposed recently. However, these methods are mainly aimed at ASIC designs. In this work, we propose a novel approximate logic synthesis method targeting at the FPGA design. We exploit the flexibility of lookup tables and propose a method that combines wire removal and local function change. The experimental results showed that our method produces better results than the state-of-the-art approximate logic synthesis method adapted to FPGA designs. Moreover, it can be combined with the state-of-the-art method to further improve the design quality.