A novel approach base on electric field analysis to reduce crosstalk problem on PCB

Parasitic capacitance between printed traces have severe influence on EMC performance of a switching power supply. A field-oriented PCB layout CAD method is proposed to reduce electric field coupling on a PCB. An emission map of a noisy trace provides a visual aid to the PCB designer. A coupling index feeds back a value to indicate coupling level between traces in real-time. A genetic algorithm based on the coupling index is implemented to obtain the best layout. A simulation and experiment are carried out to verify these ideas.